Flash memory device with word lines of uniform width and method for manufacturing thereof

ABSTRACT

A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/912,602 filed on Oct. 26, 2010, entitled “Flash Memory Device WithWord Lines of Uniform Width and Method for Manufacturing Thereof,” whichis a continuation of U.S. patent application Ser. No. 12/179,400 filedon Jul. 24, 2008, entitled “Flash Memory Device With Word Lines ofUniform Width and Method for Manufacturing Thereof,” which claimspriority from Japanese Patent Application 2007-197542 filed on Jul. 25,2007, which are hereby incorporated herein by reference in theirentirety.

TECHNICAL FIELD

The invention relates to a semiconductor device and a method formanufacturing thereof, and particularly, to a semiconductor deviceprovided with a plurality of word lines and a method for manufacturingthereof.

BACKGROUND OF THE INVENTION

The manufacture and use of semiconductor devices as non-volatile memorydevices (e.g., memory devices capable of retaining data even after powerto the device has been turned oft) have increased dramatically inresponse to recent developments in the technology. Flash memory is anincreasingly popular type of non-volatile memory. Each memory cell of aflash memory device is typically created as a transistor provided with afloating gate or an insulating film as a so-called charge storage layer.Data is recorded by storing electric charges in a charge accumulationlayer. A conventional implementation of Flash memory includes a SiliconOxide Nitride Oxide Silicon (“SONOS”) structure for storing the electriccharge in a trap layer in the Oxide film/Nitride film/Oxide film (“ONO”film) and having an insulating film as the charge storage layer.

International Application Published under the Patent Cooperation TreatyNo. 2007-013155 discloses a semiconductor device having a bit lineformed in the semiconductor substrate using the diffusion region, and aplurality of word lines which intersect with the bit line formed on thesemiconductor substrate. In the aforementioned semiconductor device, thebit line formed in the diffusion region exhibits a high resistance. Bitline contact regions are formed at each section the bit line reachesafter passing across a plurality of word lines (for example, 16 lines)for the purpose of electrically coupling between the bit line and ametal interconnection layer.

However, according to the aforementioned International Application, theproximity effect resulting from exposure of the photoresist for formingthe word line increases the width of the word line adjacent to the bitline contact region to be larger than that of the other word lines. TheInternational Application discloses a technology for providing a “dummylayer” in the bit line contact region upon formation of the word line sothat the proximity effect is suppressed. However, the width of the dummylayer is larger than that of the word line, and thus fails tosufficiently suppress the proximity effect. As a result, the width ofthe word line adjacent to the bit line contact region becomes differentfrom that of the other word lines. The width of a word line correspondsto the gate length of the transistor which forms the memory cell. Assuch, the transistor adjacent to the bit line contact region may havedifferent properties from that of other transistors in the flash memory.

SUMMARY OF THE INVENTION

The present invention was devised in light of the foregoing problems,and to provide a flash memory with an improved distribution of word linewidth.

According to one embodiment of the invention, there is provided a methodfor manufacturing a semiconductor device including the steps of forminga bit line in a semiconductor substrate, forming a plurality of wordlines which intersect with the bit line at predetermined intervals onthe semiconductor substrate, eliminating a portion of the plurality ofword lines, forming an interlayer insulating film on the semiconductorsubstrate, and forming a metal plug which penetrates through theinterlayer insulating film and is coupled to the bit line in a regionwhere the part of the plurality of word lines was eliminated.

According to another embodiment of the present invention, there isprovided a semiconductor device having a bit line formed in asemiconductor substrate, a plurality of word lines which intersect withthe bit line and are arranged at predetermined intervals on thesemiconductor substrate, and a metal plug formed in a region where aportion of the plurality of word lines is eliminated so as to be coupledto the bit line.

According to yet another embodiment of the present invention, there isprovided a semiconductor device having a bit line formed in asemiconductor substrate, a plurality of word lines formed on thesemiconductor substrate and which intersect with the bit line, and ametal plug formed between two of the plurality of word lines so as to becoupled to the bit line. The device is configured according to anequation of

L1=N×(Lw+Ls)+Ls

where L1 denotes a distance between the two of the word lines, Ls and Lwdenote a distance between word lines and a width of a word line otherthan the two of the word lines respectively, and an N denotes a naturalnumber.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part ofthis specification, illustrate embodiments of the invention and,together with the description, serve to explain the principles of theinvention:

FIG. 1 depicts an exemplary layout of a flash memory, in accordance withvarious embodiments.

FIG. 2A depicts a sectional view taken along line A-A of a first stageduring a process of manufacturing a flash memory, in accordance withvarious embodiments.

FIG. 2B depicts a sectional view taken along line B-B of a first stageduring a process of manufacturing a flash memory, in accordance withvarious embodiments.

FIG. 3A depicts a sectional view taken along line A-A in a second stageduring the process of manufacturing a flash memory of FIG. 2A, inaccordance with various embodiments.

FIG. 3B depicts a sectional view taken along line B-B in a second stageduring the process of manufacturing a flash memory of FIG. 2B, inaccordance with various embodiments.

FIG. 4A depicts a sectional view taken along line A-A in a third stageduring the process of manufacturing a flash memory of FIG. 2A, inaccordance with various embodiments.

FIG. 4B depicts a sectional view taken along line B-B in a third stageduring the process of manufacturing a flash memory of FIG. 2B, inaccordance with various embodiments.

FIG. 5 depicts a sectional view taken along line B-B in a fourth stageduring the process of manufacturing a flash memory of FIG. 2B, inaccordance with various embodiments.

FIG. 6 depicts a sectional view taken along line A-A in a fifth stageduring the process of manufacturing a flash memory of FIG. 2A, inaccordance with various embodiments.

FIG. 7A depicts a sectional view taken along line A-A in a sixth stageduring the process of manufacturing a flash memory of FIG. 2A, inaccordance with various embodiments.

FIG. 7B depicts a sectional view taken along line B-B in a sixth stageduring the process of manufacturing a flash memory of FIG. 2B, inaccordance with various embodiments.

FIG. 8 depicts a sectional view taken along line B-B in a first stageduring an alternate process of manufacturing a flash memory, inaccordance with various embodiments.

FIG. 9 depicts a sectional view taken along line B-B in a second stageduring the process of manufacturing a flash memory of FIG. 8, inaccordance with various embodiments.

FIG. 10A depicts a top view in a first stage during another process ofmanufacturing a flash memory in accordance with various embodiments.

FIG. 10B depicts a sectional view taken along line B-B in a first stageduring another process of manufacturing a flash memory in accordancewith various embodiments.

FIG. 11A depicts a top view in a second stage during the process ofmanufacturing a flash memory of FIG. 10A, in accordance with variousembodiments.

FIG. 11B depicts a sectional view taken along line B-B in a second stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 12A depicts a top view in a third stage during the process ofmanufacturing a flash memory of FIG. 10A, in accordance with variousembodiments.

FIG. 12B depicts a sectional view taken along line B-B in a third stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 12C depicts a sectional view taken along line C-C in a third stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 12D depicts a sectional view taken along line D-D in a third stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 12E depicts a sectional view taken along line E-E in a third stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 13A depicts a top view in a fourth stage during the process ofmanufacturing a flash memory of FIG. 10A, in accordance with variousembodiments.

FIG. 13B depicts a sectional view taken along line B-B in a fourth stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 13C depicts a sectional view taken along line C-C in a fourth stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 13D depicts a sectional view taken along line D-D in a fourth stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 13E depicts a sectional view taken along line E-E in a fourth stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 14A depicts a top view in a fifth stage during the process ofmanufacturing a flash memory of FIG. 10A, in accordance with variousembodiments.

FIG. 14B depicts a sectional view taken along line B-B in a fifth stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 14C depicts a sectional view taken along line C-C in a fifth stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 14D depicts a sectional view taken along line D-D in a fifth stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 14E depicts a sectional view taken along line E-E in a fifth stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 15A depicts a sectional view taken along line B-B in a sixth stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 15B depicts a sectional view taken along line D-D in a sixth stageduring the process of manufacturing a flash memory of FIG. 10B, inaccordance with various embodiments.

FIG. 16A depicts a top view in a first stage during yet another processof manufacturing a flash memory, in accordance with various embodiments.

FIG. 16B depicts a sectional view taken along line B-B in a first stageduring yet another process of manufacturing a flash memory, inaccordance with various embodiments.

FIG. 16C depicts a sectional view taken along line C-C in a first stageduring the process of manufacturing a flash memory of FIG. 16B, inaccordance with various embodiments.

FIG. 16D depicts a sectional view taken along line D-D in a first stageduring the process of manufacturing a flash memory of FIG. 16B, inaccordance with various embodiments.

FIG. 16E depicts a sectional view taken along line E-E in a first stageduring the process of manufacturing a flash memory of FIG. 16B, inaccordance with various embodiments.

FIG. 17A depicts a top view in a second stage during the process ofmanufacturing a flash memory of FIG. 16A, in accordance with variousembodiments.

FIG. 17B depicts a sectional view taken along line B-B in a second stageduring the process of manufacturing a flash memory of FIG. 16B, inaccordance with various embodiments.

FIG. 17C depicts a sectional view taken along line C-C in a second stageduring the process of manufacturing a flash memory of FIG. 16B, inaccordance with various embodiments.

FIG. 17D depicts a sectional view taken along line D-D in a second stageduring the process of manufacturing a flash memory of FIG. 16B, inaccordance with various embodiments.

FIG. 17E depicts a sectional view taken along line E-E in a second stageduring the process of manufacturing a flash memory of FIG. 16B, inaccordance with various embodiments.

DETAILED DESCRIPTION

Reference will now be made in detail to several embodiments. While thesubject matter will be described in conjunction with the alternativeembodiments, it will be understood that they are not intended to limitthe claimed subject matter to these embodiments. On the contrary, theclaimed subject matter is intended to cover alternative, modifications,and equivalents, which may be included within the spirit and scope ofthe claimed subject matter as defined by the appended claims.

Furthermore, in the following detailed description, numerous specificdetails are set forth in order to provide a thorough understanding ofthe claimed subject matter. However, it will be recognized by oneskilled in the art that embodiments may be practiced without thesespecific details or with equivalents thereof In other instances,well-known methods, procedures, and components, have not been describedin detail as not to unnecessarily obscure aspects and features of thesubject matter.

Portions of the detailed description that follows are presented anddiscussed in terms of a method. Although steps and sequencing thereofare disclosed in a figure herein (e.g., FIG. 5) describing theoperations of this method, such steps and sequencing are exemplary.Embodiments are well suited to performing various other steps orvariations of the steps recited in the flowchart of the figure herein,and in a sequence other than that depicted and described herein.

First Embodiment

Referring now to FIG. 1, FIG. 1 depicts an exemplary layout of a flashmemory, in accordance with a one embodiment. As presented in FIG. 1, bitlines 12 are formed in a semiconductor substrate 10. A plurality of wordlines 22 which intersect with the bit lines 12 are formed on thesemiconductor substrate 10. A bit line contact region 40 is formed at asection where the bit line 12 reaches after passing across a certainnumber of the word lines. In the bit line contact region 40, metal plugs28 are disposed so as to be coupled to the bit lines 12, respectively.The metal plug 28 is coupled to an interconnection layer (not shown)which extends along the direction in which the bit line 12 extends.

The word lines 22 in the area other than the bit line contact region 40are arranged at predetermined intervals. A distance L1 between adjacentword lines 22 having the bit line contact region 40 there between is thesame as a distance L2 between the word lines 22 interposing another wordline 22 there between in the area other than the bit line contact region40. The bit line contact region 40 corresponds to an area where one ofthe plurality of word lines is eliminated.

Note that the bit line contact region 40 may be the area where a portionof the plurality of word lines 22 arranged at predetermined intervals iseliminated. In other words, the distance L1 may satisfy the followingequation:

L1=N×(Lw+Ls)+Ls (N: natural number)

where the Lw and the Ls denote the width of the word line 22 and thedistance between the adjacent word lines 22 in the area other than thebit line contact region 40 respectively.

Referring to FIGS. 2A to 7B, the method for manufacturing the flashmemory according to the first embodiment will be described. Referring toFIGS. 2A and 2B, a tunnel oxide film 14 as a silicon oxide film, a traplayer 16 as a silicon nitride film, and a top oxide film 18 as thesilicon oxide film are sequentially formed on the p-type semiconductorsilicon substrate 10 (or the p-type region in the semiconductorsubstrate). As a result, an ONO film 20 is formed on the semiconductorsubstrate 10 as the charge storage layer. The arsenic ion implantationis performed into the semiconductor substrate 10 to form the bit lines12 each formed of the n-type diffusion area. FIG. 2A is a sectional viewof the bit line 12 in the lateral direction. FIG. 2B is a sectional viewof the bit line 12 in the direction in which it extends.

Referring here to FIGS. 3A and 3B, a conductive layer 21 formed ofpolysilicon, which is to be the word lines, is applied onto thesemiconductor substrate 10 via the ONO film 20 through the ChemicalVapor Deposition (“CVD”) process, for example. A photoresist 50 is thenapplied onto the conductive layer 21. The photoresist 50 is formed withthe stripe patterns at predetermined intervals through the exposuretechnology.

Referring now to FIGS. 4A and 4B, the conductive layer 21 is etchedusing the photoresist 50 with the patterns as the mask such that aplurality of word lines 22 intersecting with the bit lines 12 are formedat predetermined intervals.

Referring to FIG. 5, a photoresist 52 is applied onto the semiconductorsubstrate 10 so as to cover the word lines 22. An opening 56 is formedthrough the exposure technology so as to expose a word line 22 a(indicated by the broken line in FIG. 5) among the plurality of wordlines 22. The exposed word line 22 a is etched to be eliminated. Thearea corresponding to the eliminated word line 22 a becomes the bit linecontact region 40. Accordingly, the distance L1 becomes equal to thedistance L2.

Referring to FIG. 6, a second insulating layer 24 is formed of thesilicon nitride so as to cover the word lines 22. Performing the etchback forms a side wall as the second insulating layer 24 formed at theside of the word line 22. In the area other than the bit line contactregion 40, the interval between the word lines 22 is so small that thesecond insulating layer 24 at the side of the adjacent word line 22 isintegrated therewith. Meanwhile, in the bit line contact region 40, theinterval between the word lines 22 is large, thus forming an area wherethe second insulating film 24 is not formed.

Referring to FIGS. 7A and 7B, an interlayer insulating film 26 formed ofthe silicon oxide film, for example, is applied onto the semiconductorsubstrate 10 via the ONO film 20, the word lines 22, and the secondinsulating layers 24. In the bit line contact region 40, a contact holecoupled to the bit line 12 is formed in the interlayer insulating film26. Metal plug 28 is formed in the contact hole using a metal such astungsten. An interconnection layer 30 coupled to the metal plug 28 isformed on the interlayer insulating film 26. The interconnection layer30 is formed of the metal, and extends along the direction in which thebit line extends. A protection film 32 is formed so as to cover theinterconnection layer 30. In this manner, the flash memory according tothe first embodiment is completed.

According to the first embodiment, the photoresist 50 (mask layer) withthe patterns at predetermined intervals are formed on the conductivelayer 21 as shown in FIG. 3B. This makes it possible to suppress theproximity effect upon the exposure, and to allow each width of therespective patterns to be substantially the same. Accordingly, theconductive layer 21 is eliminated using the photoresist 50 as the masksuch that the plurality of word lines 22 are formed at predeterminedintervals as shown in FIG. 4B. Thereafter, the word line 22 a as aportion of the plurality of word lines 22 is eliminated to form the bitline contact region 40 as shown in FIG. 5. As described above, the wordline 22 adjacent to the bit line contact region 40 may be formed to havesubstantially the same width as that of the other word line 22. Thismakes it possible to suppress the distribution of the property of thetransistor which forms the memory cell. Note that while FIG. 5 showsthat the single word line 22 a is eliminated, in alternate embodimentstwo or more word lines may be eliminated.

Second Embodiment

In a second embodiment, second insulating layers are formed among theplurality of word lines, and the part of the word lines is eliminatedafter the formation of the second insulating layers. Referring thus toFIG. 8, the second insulating layers 24 each formed of the siliconnitride are formed so as to cover the word lines 22 after the formingstep thereof, as shown in FIGS. 4A and 4B. The upper surface of the wordline 22 is exposed through the etch back, and each space between theword lines 22 is filled with the second insulating layer 24.

Referring to FIG. 9, a photoresist 52 is applied onto the semiconductorsubstrate 10 so as to cover the word lines 22. The opening 56 is formedso as to expose one word line 22 a (shown by the broken line in FIG. 9)among the plurality of word lines 22 through conventional exposuretechnology. The exposed word line 22 a and the second insulating layers24 in the vicinity thereof are etched to be eliminated. The areacorresponding to the eliminated word line 22 a and the second insulatinglayers 24 becomes the bit line contact region. This allows the distancesL1 and L2 to be equal. Thereafter, the step of the first embodiment asshown in FIGS. 7A and 7B is performed to complete production of theflash memory according to the second embodiment.

In the first embodiment herein described, upon formation of the secondinsulating layer 24 shown in FIG. 6, each of the second insulatinglayers 24 in the bit line contact region 40 has a different crosssectional shape from that of the second insulating layer 24 between theword lines 22 in the area other than the bit line contact region 40.Accordingly, the stress from the second insulating layer 24 exerted tothe word line 22 adjacent to the bit line contact region 40 is differentfrom the one exerted to the other word line 22. Consequently, thetransistor adjacent to the bit line contact region 40 has the differentproperty from that of the other transistor. In the second embodiment,upon formation of the second insulating layer 24 as shown in FIG. 8,each cross section of all the second insulating layers 24 hassubstantially the same shape. Consequently, the stress exerted to theword line 22 becomes uniform, resulting in a greater uniformity amongstthe transistors.

Third Embodiment

In a third embodiment, the word line is formed of first and secondconductive layers. The method for manufacturing a flash memory accordingto the third embodiment will be described referring to FIGS. 10A to 14B.Referring first to FIGS. 10A and 10B, the ONO film 20 formed of thetunnel oxide film 14, the trap layer 16 and the top oxide film 18 isapplied onto the semiconductor substrate 10. A first conductive layer 60formed of polysilicon is applied onto the semiconductor substrate 10 viathe ONO film 20. Each area of the first conductive layers 60 where thebit line is to be formed is eliminated to form an opening 80 such thatthe resultant first conductive layers 60 are arranged in the stripestate. The arsenic ion implantation is performed into the semiconductorsubstrate 10 using the first conductive layer 60 as the mask.Consequently, the bit lines 12 are formed in the semiconductor device10.

Referring next to FIGS. 11A and 11B, first insulating layers 62 eachformed of the silicon oxide film are formed so as to cover the firstconductive layer 60. The first insulating layer 62 is polished through aChemical Mechanical Polish (CMP) process so as to be formed on the bitline 12 between the first conductive layers 60. The bit line 12 and thefirst insulating layer 62 are formed in a self alignment manner. Asecond conductive layer 64 formed of polysilicon is applied onto thefirst conductive layers 60 and the first insulating layers 62.

Referring to now FIGS. 12A to 12E, a photoresist 70 (mask layer) withpatterns at predetermined intervals is formed on the second conductivelayers 64. The second conductive layer 64 and the first conductive layer60 are etched to be eliminated using the photoresist 70 as the mask. Theplurality of word lines 65 are formed from the first and the secondconductive layers 60 and 64 so as intersect with the bit lines 12.Referring to FIG. 12B, in the area where the word line 65 is formed, thefirst insulating layer 62 and the second conductive layer 64 are formedon the bit line 12, and the first conductive layer 60 and the secondconductive layer 64 are formed between the bit lines 12. The firstconductive layer 60, formed directly on the ONO film 20, serves as agate electrode between the bit lines 12.

Referring to FIG. 12C, the first insulating layer 62 is left on the bitline 12 between the word lines 65. Meanwhile, the first and the secondconductive layers 60 and 64 are eliminated. Referring to FIG. 12D, inthe region where the bit line 12 is formed, the first insulating layer62 extends along the direction in which the bit line 12 extends.Referring to FIG. 12E, the first insulating layer 62 is not formedbetween the bit lines 12.

Referring to FIGS. 13A to 13E, a portion of the plurality of word lines65 is eliminated. Consequently, the bit line contact region 40 isformed.

Referring to FIGS. 14A to 14E, second insulating layers 68, each formedof the silicon nitride, are formed through the high density plasma CVDprocess so as to cover the word lines 65 and the first insulating layers62. The second insulating layers 68 are then etched back. Therefore,side walls each formed as the second insulating layer 68 are formed atthe bit line contact region 40 side of the word line 65 adjacent to thebit line contact region 40. Meanwhile, the area between the word lines65 other than the bit line contact region 40 is filled with the secondinsulating layer 68.

Referring to FIGS. 15A and 15B, the interlayer insulating films 26 eachformed of the silicon oxide film are applied so as to cover the wordline 65, the first insulating layers 62 and the second insulating layers68. The metal plug 28 coupled to the bit line 12 while penetratingthrough the interlayer insulating film 26 is formed in the bit linecontact region 40. The interconnection layer 30 coupled to the metalplug 28 is applied onto the interlayer insulating films 26. Theprotection film 32 is further formed to cover the interconnection layer30, thus completing production of the flash memory according to thethird embodiment.

In the third embodiment, the photoresist 70 (mask layer) with thepatterns at predetermined intervals is formed on the second conductivelayer 64 as shown in FIGS. 12A to 12E. This makes it possible tosuppress the proximity effect upon the exposure, thus making the widthof each of the patterns substantially the same. Accordingly, theplurality of word lines 65 may be formed at uniform intervals upon theformation thereof by eliminating the second and the first conductivelayers 64 and 60 using the photoresist 70 as the mask. Thereafter, thebit line contact region 40 may be formed by eliminating a portion of theplurality of word lines 65 as shown in FIGS. 13A to 13E. In the casewhere the word line 65 is formed of the first and the second conductivelayers 60 and 64, the word line 65 adjacent to the bit line contactregion 40 may have substantially the same width as that of the otherword line 65.

Fourth Embodiment

In a fourth embodiment, the second insulating layers are formed amongthe plurality of word lines, and a portion of the word lines iseliminated after forming the second insulating layers. Referring firstto FIGS. 16A to 16E, the second insulating layers 68 each formed of thesilicon nitride film are formed through the high density plasma CVDprocess so as to cover the word lines 65 and the first insulating layers62 after performing the step according to the second embodiment shown inFIGS. 12A to 12E. The second insulating layers 68 are etched back toexpose the upper surfaces of the word lines 65. Accordingly, the secondinsulating layer 68 may be filled between the word lines 65.

Referring next to FIGS. 17A to 17E, a portion of the plurality of wordlines 65 is eliminated. Consequently, the bit line contact region 40 isformed. Thereafter, the step according to the third embodiment shown inFIGS. 15A and 15B is performed to complete production of the flashmemory according to the fourth embodiment.

As described in the third embodiment, the second insulating layer 68 inthe bit line contact region 40 in the forming step thereof as shown inFIGS. 14A to 14E has a different cross sectional shape than that of thesecond insulating layer 68 between the word lines 65 in the area otherthan the bit line contact region 40. Likewise, as described in the firstembodiment, the stress from the second insulating layer 68 exerted onthe word line 65 adjacent to the bit line contact region 40 is differentfrom the one exerted on the other word line 65. However, in the fourthembodiment as shown in FIG. 16A to 16E, every cross sectional shape ofthe second insulating layers 68 becomes substantially the same in theforming step thereof. Therefore, the uniform stress is exerted on theword line 65, resulting in a more uniform transistor property.

In the above described embodiments, a case where an ONO film 20 isimplemented as the charge storage layer formed on the semiconductorsubstrate 10, and the word lines 22 or 65 are formed on the ONO film 20has been described. However, formation of the charge storage layer isnot limited to such. For example, the charge storage layer may also beformed at the side of the word line 22.

Although the subject matter has been described in language specific tostructural features and/or methodological acts, it is to be understoodthat the subject matter defined in the appended claims is notnecessarily limited to the specific features or acts described above.Rather, the specific features and acts described above are disclosed asexample forms of implementing the claims.

1-9. (canceled)
 10. A semiconductor device comprising: a bit line formedin a semiconductor substrate; a plurality of word lines, wherein theplurality of word lines is arranged at predetermined intervals on thesemiconductor substrate and intersects with the bit line; and a metalplug formed in a region where a portion of the plurality of word linesis eliminated so as to be coupled to the bit line.
 11. The semiconductordevice of claim 11, further comprising an interlayer insulating filmformed on the semiconductor substrate.
 12. The semiconductor device ofclaim 11, further comprising a first insulating layer that is formed onthe bit line between first conductive layers.
 13. The semiconductordevice of claim 13, further comprising second insulating layers formedamong the plurality of word lines.
 14. The semiconductor device of claim11, further comprising a charge storage layer formed on thesemiconductor substrate.